Timing recovery units perform clock recovery and data retiming functions. Well known timing recovery schemes include a phase-locked loop (PLL). The PLL is basically a closed loop frequency control system, which operates by producing an oscillator frequency to match the frequency of an input signal. In this locked condition, any slight change in the frequency of the input signal first appears as a change in phase between the input signal frequency and the oscillator frequency. This phase shift then acts as an error signal to change the frequency of a local PLL oscillator to match the input signal frequency. The locking onto a phase relationship between the input signal frequency and the local oscillator accounts for the name phase-locked loop.
FIG. 1A illustrates a prior art timing recovery unit 10 as part of a high-speed transceiver, which provides receiver clocks that are synchronized to an incoming signal. The timing recovery unit 10 comprises a clock multiplying unit 15 including a voltage-controlled oscillator (VCO) 20, and a PLL loop 25 comprising a phase detector 30, a loop filter 40 and a phase interpolator 50. The clock multiplying unit 15 takes a reference clock and speeds it up to a high frequency. The VCO 20 is thus locked to the reference clock. A phase interpolator 50 takes the phase from the VCO 20 and shifts the phase either forward or backward to track frequency as well as phase from a received (Rcvd) signal. An output clock of the phase interpolator 50 drives a phase detector 30 which compares the output clock to the received signal and generates output current pulses proportioned to the phase error between them. The output current pulses are filtered and integrated by a loop filter 40 to generate a voltage.
FIG. 1B illustrates a prior art implementation of the timing recovery unit of FIG. 1A. A quadrature low frequency analog oscillator 60 is provided to control a phase interpolator 70. The oscillator 60, which receives an input voltage, can operate from a positive frequency to a negative frequency. Phase interpolation is then performed to output a high speed recovery clock aligned with an incoming high speed signal. A benefit of this implementation is that the control elements are low frequency devices, and both the control oscillator 60 and the phase interpolator 70 are designed in analog form. A problem with this implementation, however, is that when the phase is “locked”, the control oscillator 60 has to maintain that phase perfectly in perpetuity. Due to variations in manufacturing and introduction over many units, mismatches and imperfections degrade performance. The control oscillator 60 can cause phase errors induced by supply or substrate noise that can accumulate over many clock cycles. At higher frequencies, overload and saturation of the control oscillator 60 can affect the stability of the system. Leakage, drifts in frequencies, and other sensitivities caused by analog devices in prior art PLL's degrade performance and bit error rate (BER) targets.
What is needed is a PLL-based timing recovery unit that avoids sensitive analog circuitry, increases yield, and provides digital programmability in the system and preferably on the same integrated circuit chip. What is also needed is a timing recovery unit using both analog and digital devices to modulate phase and achieve sub-picosecond phase resolution in a timing recovery unit. What is also needed is a timing recovery unit that uses both analog and digital techniques on a single integrated circuit to convert a high precision digital word into a high precision analog value while preventing an overload or saturation condition.